This book discusses in detail low-voltage low-power designs for minimizing the hardware resources required by neural network implementations. The novel method presented in this book for an accurate realization of activation functions for artificial neural networks (ANNs), is based on specific superior-order approximation functions. The author describes analog implementations in CMOS technology to increase the speed of operation, while reducing the hardware resources required for obtaining these approximation functions. Original architectures presented in this book, used for implementing previous CMOS computational structures, allow for operation independent of technological errors and temperature variations. SPICE simulations confirm the theoretically estimated results for previously presented CMOS computational structures, developed for ANNs and artificial intelligence applications.
